In the structure of silicon wafers and silicon substrates for dies, packaging substrates, fan-out packaging and other devices, metal lines are used inside the silicon structure to connect different devices together. The lines are usually copper but are made from other conductors for specific applications. Typically the lines are arranged in horizontal layers to connect devices at each layer together. To connect devices at different layers, a vertical via that connects two horizontal lines is formed. For devices that are built up in layers by photolithography and similar types of processes common in the construction of silicon micro devices, the horizontal layers are easily formed as the device is built up. Similar approaches are used for micro devices made from other materials.
The metal lines act as wire conductors and are subject to all of the same effects as any other wire conductor. The metal lines will have a resistance, a capacitance, an inductance, and a range of other transient and third order effects. If the metal lines are too close together, then current passing through one line will induce effects in nearby lines through the shared capacitance, inductance and other effects. At high frequencies, cross-talk develops in which a signal in one line generates a similar but weaker signal in the nearby line. Cross-talk and other similar effects are typically avoided and may be reduced by separating the metal lines with insulators and some physical distance. The insulator prevents actual electron flow from one metal line to the other and the physical distance reduces the electromagnetic coupling between the wires so much so that it can be ignored.